The projects in this blog utilize the Blog LTspice equivalent Level 3 Spice, with constant output conductance over the full range of drain source voltage. The derivation is periodically considered. NMOS Amplifier Stage - LTspice Blog Level 3 Review. MathCAD Compare Post Sat Region Modulators Parameters m and lc. Match Id - vds slope, pre-sat and sat, at vds = VDsat Id and Id3 (standard) converge as vds approaches infinity. Equate lc functions. Solve for parameter m, for a given VDsat (Vg) Find vd for gate width W = 10 um, and then iD. LabVIEW Iteration Function. Iterate to set sum of currents at vd node = zero (approximately). At solution. Function f = iD - ir. LabVIEW Circuit - Gate vg is applied with Global Variable. Iteration variable vd is assigned to Global Variable here. Iteration Program This program indicates the convergence rate for an init vd = 1 V and vg = -1.58 V. The values are init followed by vd outputs for index = 0,1,2. DC Sweep Lower Plot is LabVIEW DC Transfer a...
