MOSFET Circuits - Level 3 Spice with Constant Output Conductance versus Drain-Source Volts - ETA Effect
POST Circuit - Pspice Schematics Common-Source Gain Stage This Simulator Version is Based on the ETA Effect (a function of vgs, in this case) in Pre-Sat Parameter fs is from the XJ effect. VTo is the threshold voltage at vds = 0, and VT is, for this simulator, for a value of vds in Pre-Sat. Voltage Vdsat is variable sat voltage at a given vds. Vdsatp is the variable sat voltage at Sat-Post Sat. Pre-Sat Drain Current LabVIEW Simulation - In vds Saturation Asm is the ratio of this simulator and Level 3 Standard at VDsat. This precision form for Lp is discussed in the following (Eq. 6.2.1): (Operation and Modeling of the MOS Transistor, 2nd Edition, Yannis Tsividis, McGraw-Hill) LabVIEW for both Simulators Read Pspice Schematics DC Sweep of POST Circuit